Area Efficient Radix 4 2 64 Point Pipeline FFT Architecture Using Modified CSD Multiplier

F. Siddiq, H. Jamal, T. Muhammad, M. Iqbal


A modified Fast Fourier Transform (FFT) based radix 42 algorithm for Orthogonal Frequency Division Multiplexing (OFDM) systems is presented. When compared with similar schemes like Canonic signed digit (CSD) Constant Multiplier, the modified CSD multiplier can provide a improvement of more than 36% in terms of multiplicative complexity. In Comparison of area being occupied the amount of full adders is reduced by 32% and amount of half adders is reduced by 42%. The modified CSD multiplier scheme is implemented on Xilinx ISE 10.1 using Spartan-III XC3S1000 FPGA as a target device. The synthesis results of modified CSD Multiplier on Xilinx show efficient Twiddle Factor ROM Design and effective area reduction in comparison to CSD constant multiplier.

Full Text:



W. Han, A. T. Erdogan, T. Arslan and M. Hasan, ETRI Journal

(2008) 451.

J. G. Proakis and D. G. Manolakis, Digital Signal Processing,

Prentice Hall of India Private Limited (2003).

A. Saeed, M.Elbably, G. Abdelfadeel and M.I. Eladawy, Int. J.

of Circuits, Systems and Signal Processing 3 (2009) 103.

K. Harikrishna, T.R. Rao and. V.A. Labay, An Efficient FFT

Architecture for OFDM Communication Systems, Asia Pacific

Microwave Conference (APMC), Singapore, 7-10 Dec. (2009)

U. Rashid, F. Siddiq, T. Muhammad and H. Jamal,

The Nucleus 50 (2013) 301.

J.W. Cooley and J.W. Tukey, Math. Computation 19 (1965)

Chi-hau Chen, Signal Processing Handbook, CRC Press (1988).

L. Jia, Y. Gao, J. Isoaho and H. Tenhunen, A New VLSI

Oriented FFT Algorithm and Implementation, Proceedings of Eleventh Annual IEEE International ASIC Conference (1998)

p. 337.

M. Hasan, T. Arslan and J.S. Thompson, IEEE Transaction on

Consumer Electronics 49 (2003) 128.

User Guide “FFT MegaCore Function,” Version 8.1, Altera

Corporation. Available: http://www., Nov. (2008).

E.E. Swartzlander, VLSI Signal Processing Systems, Kluwer

Academic Publishers (1998).

Amphion.CS246064-Point Pipelined FFT/IFFT; Available

from: 64-Point-datasheet.

html (2002).

Y. Jung; H. Yoon and J. Kim, IEEE Transactions on Consumer

Electronics 49 (2003) 14.

W. Han, T. Arslan, A. T. Erdogan and M. Hasan, Proc. IEEE

Int. Conf. on Acoustics Speech and Signal Processing 5 (2005)

S. He and M. Torkelson, Designing Pipeline FFT Processor for

OFDM (de) Modulation, Proc. IEEE URSI Int. Symp. Sig.

Syst. Electron (1998) 257.

L. Jia, Y. Gao, Jouni and H. Tenhunen, A New VLSI-oriented

FFT Algorithm and Implementation, IEEE International ASIC

Conf.(1998) 337.

Jung-yeol Oh and Myoung-Seob Lim, Area and Power

Efficient Pipeline FFT Algorithm, IEEE Workshop on Signal

Processing Systems Design and Implementation (2005) 520.

J.Y. Oh, J. S. Cha, S. K. Kim and M. S. Lim, Implementation of

Orthogonal Frequency Division Multiplexing using radix-N

Pipeline Fast Fourier Transform (FFT) Processor, Jpn. J. Appl.

Phys. 42 (2003) 1.

K.K. Parhi, VLSI Digital Signal Processing Systems, John

Wiley & Sons, Inc., USA (1999).

W. C. Yey and C. W. Jen, IEEE Trans. Sig. Proc. 51 (2003)

S. M. Kim, J. G. Chung and K. K. Parhi, IEEE Int. Symp. Cir.

Syst. (2002) 69.

K.J. Cho, K.C. Lee, J.G. Chung and K.K. Parhi, IEEE Trans.

VLSI Syst.12 (2004) 90.


  • There are currently no refbacks.